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CoWoS Doubling, Intel EMIB-T & CIA-Beijing Escalation
Audio is available on Spreaker — see link below.
TSMC's CoWoS packaging capacity doubles to 260K wafers/month by 2028 — and that constraint now matters more than process node leadership. Plus Intel's EMIB-T challenge, HBM4 yield risks, and how CIA-Beijing tensions are reshaping semiconductor supply chains.
Audio is available on Spreaker — see link below.
TSMC just confirmed it's doubling CoWoS packaging capacity to two hundred sixty thousand wafers per month by end of twenty twenty-eight, and that single announcement tells you more about where the AI supply chain is actually breaking than anything happening at the leading-edge node. Here's the key distinction.
TSMC currently runs about one hundred thirty thousand CoWoS wafers per month. The plan is to reach two hundred sixty thousand by twenty twenty-eight, with expansion happening across its AP7 facility in Taiwan and its Arizona operations.
Intel is not standing still. Its EMIB-T packaging technology is estimated to reach forty to forty-five thousand wafers per month by twenty twenty-eight.
Packaging capacity isn't the only constraint running parallel to the node conversation. HBM4 yield, heat dissipation, and stacking reliability are all limiting factors in AI accelerator production cadence heading into twenty twenty-six.
On the geopolitical side, a confrontation that's been building quietly just became public. The CIA director named Chinese AI and semiconductor companies as explicit intelligence collection priorities.
That summit is the next real watchpoint. The outcome could reset semiconductor trade barriers or harden them further.
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